This invention relates to tile byte and frame alignment of a high-speed serial data signal such as a synchronous optical network (SONET) signal.
A SONET signal is divided into frames, each of which begins with a synchronization pattern (hereinafter referred to as a sync pattern). A frame aligner in the receiving apparatus searches the incoming tiara For the sync pattern, and after finding the sync pattern, checks that the sync pattern recurs at intervals equal to the frame length. By detecting the position of the sync pattern, the frame aligner can correctly separate the serial data into bytes (byte alignment) and group these bytes into frames (frame alignment).
The ideal way to detect a sync pattern is to shift the incoming signal bit by bit through a shift register having the length of the sync pattern, testing the register contents against the sync pattern at every shift. Unfortunately, this becomes difficult at the speeds typical of synchronous optical transmission systems, which may exceed a gigabit per second. Accordingly, the serial data signal is commonly demultiplexed prior to sync pattern detection. A one-to-eight demultiplexer, For example, converts the serial signal to byte-wide data and enables the frame aligner to operate at one-eighth-the line speed.
A conventional Frame aligner of this type has a byte shifter that receives and shifts incoming data a byte at a time. Since the incoming data are not necessarily aligned on correct byte boundaries, the capacity of the byte shifter is one byte more than the length of the sync pattern. The sync pattern is tested against the contents of the byte shifter at eight possible byte alignments. When a sync pattern is detected, it is used to select one of these alignments, thereby producing correctly byte-aligned output data. Correct alignment of subsequent frames is checked by testing for the presence of the sync pattern at the beginning of each frame.
A problem with this conventional method of byte and frame alignment is the large size of the byte shifter, which takes up excessive space and dissipates excessive power. A four-byte sync pattern, for example, requires a Five-stage byte shifter typically comprising forty flip-flop circuits. An associated problem is the large circuit needed to compare the byte shifter contents with the entire sync pattern at eight possible byte alignments. The size of this circuit becomes an impediment to high-speed operation.